A. Technical Field
The present invention relates generally to digital circuit design, and more particularly, to the design of volatile circuits that contain volatile data states that may be lost without the continued application of applied power. An example of such a volatile circuits are digital memory circuits capable of retaining the data state of each memory cell during power-down periods in which the primary power source for the memory circuit is uncoupled from the memory circuit or, otherwise, interrupted or rendered inactive to the memory circuit. A particular example of such a memory circuit is a random access memory (RAM) circuit.
B. Background of the Invention
An ongoing trend to reduce the size of the components or elements or devices in digital integrated circuits is leading to geometries that enable the operation of circuits having volatile circuit elements, such as, for example, memory cells, flip flop devices, etc., using a lowered power level of about 1.8 volts. Power at this level is typically provided from a conventional unregulated external power source of about 3.0+/−10% volts using an internal low dropout (hereinafter “LDO”) power supply regulator. Nonetheless, when such low voltage devices are inactive or turned off, the leakage currents exhibited are substantially large relative to the same kind of devices configured using earlier versions of CMOS technology. Such earlier devices typically operate from an unregulated external power source of about 3.0 volts with lower leakage current.
In modern CMOS processes, adequately low standby currents cannot be achieved simply by making all circuit nodes in such a circuit design static because of these excessive leakage currents in smaller geometry devices when placed in an “off” or inactive state. Previous solutions to this problem have concentrated on employing analog circuit techniques to reduce these leakage currents. Examples of these techniques are the employment of a reverse substrate bias and the interposition of much less leaky high voltage transistors in each leakage path, such as employing thicker gate oxide, deeper junctions, and larger dimension devices, such as transistor components or elements. These solutions are complex and do not guarantee the desired results.
What is need is a way to provide for memory circuit backup of their volatile memory states with respect to newer lower voltage operating CMOS circuits employing an approach that provides for lower leakage during periods of circuit power extension or turn-off. The approach here utilizes digital circuit state retention in the absence of normal circuit power or inactivation.